VT6518 Ethernet Switch Controller with 16 Ports of 10/100BaseT/TX and 2 Ports of 10/100/1000BaseT/TX PRODUCT FEATURES: - Single-chip low-power non-blocking store-and-forward shared- memory layer-2 switched Ethernet controller with sixteen 10/100BaseT/TX ports and two 10/100/1000BaseT ports, embedded 4Mbit memory for packet buffers and control data. - High-performance switching engine performs forwarding and filtering at full wire speed, maximum 148,810 packets/sec on each 100Mbps Fast Ethernet port, and maximum 1,488,100 packets/sec on each 1000Mbps Gigabit Ethernet port. - Provide SMII and SS-SMII interface for the sixteen 10/100BaseT/TX ports to connect with two Octal PHY devices. - Two 802.3z and 802.3ab compliant Gigabit Ethernet ports with GMII interface to connect with Gigabit PHY devices and integrated Physical Coding Sublayer (PCS) logic to provide direct interface TBI to Gigabit SERDES transceivers. Each Gigabit port can also be configured as a 10/100Mbps MII port - Supports chip initialization via strapping or 2-pin EEPROM interface. CPU initialization is supported but not required. - Supports SMI auto-polling for configuring speed, duplex mode, and 802.3x flow control capability for each Ethernet port to enable plug-and-play operation. Any Ports can be in disable mode, force mode or auto-polling mode. - Supports auto-negotiation for configuring speed, duplex mode, and 802.3x flow control capability for each gigabit Ethernet port with (full duplex only) TBI interface. - Supports 802.3x flow control for full-duplex ports. Supports collision-based and carrier-based backpressure for half-duplex ports. - Supports Head of Line (HOL) blocking prevention. - Supports broadcast storm filtering. - Embedded 3Mbit SSRAM for packet data, including 3072 packet buffers of 128 bytes. The buffer link node is embedded in the 16- byte tail of packet buffer. - Programmable maximum Ethernet frame length of range from 1518 to 1568 bytes. - Embedded 1Mbit SSRAM for control data, including 6/8/10/14K address table entries, 1/2/4K VLAN table entries, 256 IP multicast table entries, 1K protocol-based VLAN index table entries, and 29 MIB counters per port. - Efficient self-learning and address recognition mechanism enables forwarding rate at wire speed. - Support both direct and CRC-map hashing algorithms. - Auto-aging with programmable inter-age time. - Supports port-based VLAN, 802.1q tag-based VLAN with either IVL or SVL. - Supports 802.1v protocol-based VLAN classification. - Supports 802.1x port-based network access control. - Supports 802.1s Multiple Spanning Trees. - Fast address migration to support 802.1w Rapid Reconfiguration. - Supports IP Multicasting to implement IGMP snooping function. - Supports 802.1p Class of Service with 2-level priority queueing. - Supports three scheduling schemes: FCFS, strictly priority scheduling and weighted round robin scheduling. Each one has an option of delay bound control. - Supports by-port Egress/Ingress rate control with minimum resolution of 1 packet per 10ms. - Supports 802.3ad port trunking with flexible load distribution control and fail-over function. - Provides flexible trunk grouping within 18 ports, up to 4 ports per trunk group. - Supports source-based, destination-based, and source- destination-pair-based Sniffer function. - Support ingress port security mode, incoming packets with unknown source MAC could be dropped or captured to CPU. - Supports maximum bridge transit delay bound control. - Supports 16-bit CPU interface for 8/16-bit IDE, ARM with DMA (single/block/ demand mode), 80186 with DMA (single/block mode) for management and SOHO router applications. - Provides 29 counters per port to support MIB II-RFC1213 (RMON groups 1,2,3,9), RFC1493 (Bridge-MIB), RFC1643(Ether-Like). - Supports RMON sampling with sampled packet error indication. - Provides serial LED display for port status, buffer/bandwidth utilization, broadcast storm alert, and power-on embedded memory BIST indication. - With an internal oscillator and PLL, only a low-cost 25MHz external crystal is required to provide Internal system clock of 62.5Mhz, SRAM/GMII/SMII/SS-SMII clock of 125Mhz. It provides 125MHz clocks output for SMII to reduce system cost. - 2.5V core, 3.3V pad, TSMC 0.22mm CMOS process, 208-pin LQFP package with exposed PAD to facilitate power spreading.